1. Field of the Invention
The present invention relates to designing integrated circuits to increase reliability. More specifically, the present invention relates to designing integrated circuits to reduce failures due to electromigration.
2. Description of the Related Art
The reliability of recent very large scale integration (also referred to as xe2x80x9cVLSIxe2x80x9d) designs has been improved through better alloys, additional layers and increasing grain size. However, designers continue to have aggressively pursue increased product performance. Pursuing increased performance leads to higher clock speeds and power dissipation, which increase thermal density and thermal stress. High current densities and thermal stresses drive degradation mechanisms in the interconnect system of VLSI circuits. Specifically, high current densities lead to electromigration-caused failures.
Electromigration (also referred to as xe2x80x9cEMxe2x80x9d) is an atomic diffusion phenomenon and refers to the transport of ions or atoms due to the high current densities and/or strong electric fields. Electromigration is a temperature activated process. Therefore, temperature will influence the amount and speed of migration of ions and atoms. FIG. 1A illustrates the mechanics of electromigration. As shown in FIG. 1A, electric current leaves the metal strip at the anode and is conducted to the cathode. The electrical current causes metal particles to migrate from the cathode side of the strip to the anode side of the strip. By definition, the electrical current is in the opposite direction to the electron flow. Thus, metal particles deplete the cathode side of the metal strip and accumulate on the anode side. Depletion of the cathode side can cause voids which can cause an open circuit. Accumulation on the anode side can lead to a hillock which can cause a short circuit. Thus, both accumulation and depletion can cause failure of a microprocessor or other integrated circuit.
Referring briefly to FIG. 2, an equation is provided to calculate the outgoing atomic flux per unit volume, referred to as the volumetric generation rate (∇xc2x7{right arrow over (J)}A). As illustrated in FIG. 2, the equation can be used to calculate the volumetric generation rate due to a structural inhomogeneity, a temperature inhomogeneity, a current density inhomogeneity or a material inhomogeneity. For example, current density inhomogeneity can be caused by two imposed currents on a single metal lead with a single anode and a single cathode. Flux divergence is the difference between flux received and flux transmitted. In structural inhomogeneity, flux is not transmitted evenly due to voids or other structural imperfections in the metal lead. The depletion and accumulation regions are not bound to the cathode or anode. These processes take place wherever an inhomogeneity causes a volumetric generation rate greater than zero.
FIG. 2 also depicts temperature inhomogeneity. The temperature inhomogeneity leads to an inhomogeneous atomic flux distribution which causes areas of depletion and accumulation of atoms. Finally, FIG. 2 also represents the inhomogeneity due to mature constants. An inhomogeneity in the flux can be caused by an inhomogeneity of material constants. For example, inhomogeneity due to constants such as conductivity and diffusivity. These constants can be due to barrier layers between metals such as aluminum and copper in the metal lead.
As previously discussed (refer to FIG. 1A), the transport of ions or atoms causes degradation and failure of metal connections in an integrated circuit. Thus, EM has remained a key variable in the design of integrated circuits. Designers compare interconnect direct charge average current per unit width, Jxe2x80x2eff, to a fixed limit. For example:   S  =            Actual      ⁢              xe2x80x83            ⁢              J        eff        xe2x80x2                            Design        ⁢                  xe2x80x83                ⁢        Limit        ⁢                  xe2x80x83                ⁢                  J          eff          xe2x80x2                    ⁢              xe2x80x83            
where:
S represents current density ratio
Jxe2x80x2eff represents electrical current density per unit width in amps per centimeter
With appropriate modifications for contacts and alternating current lines the equation given above can be used to provide a conservative fixed limit. Previously, designers considered a design with S less than 1 a reliable design. Typically, designs producing S greater than 1 have been subject to redesign.
However, from a reliability perspective, EM is inherently statistical. Failure times can vary widely for identically sized and stressed interconnects. An approach that factors EM failure statistics into the setting of EM design limits does not quantify chip reliability and does not reveal the relationship between S and EM risk. When reliable design is defined to mean achieving a chip-level reliability goal, fixed current density design limits become mathematically arbitrary. A design which has all interconnects to satisfy S less than 1 does not guarantee a reliable design. Similarly, a design including an interconnect with S greater than 1 does not necessarily lead to an unreliable product. The total statistical risk is the critical variable in the design. Therefore, if each segment of interconnect at each stress level can be evaluated, the reliability goal can be distributed between interconnections. Distributing the reliability goal among classes of interconnections minimizes the performance limitation that an EM reliability goal places on the design.
Table 1 (below) demonstrates a typical non-linear relationship between maximum allowed current density and the number of violation corrections needed to reduce the current density below the allowable limit for a specific design.
Table 1 demonstrates that nine leads in the integrated circuit block must be redesigned (by widening the lead or other modification) to satisfy the current density limit of 3.17xc3x97106 amps per square centimeter. Similarly, for a current density of 2.58xc3x97106 amps per square centimeter, seventeen leads in the hypothetical integrated circuit block must be redesigned. Thus raising the allowable current density limit from 2.58xc3x97106 amps per square centimeter to 3.17xc3x97106 amps per square centimeter decreases from seventeen to nine the number of violations which must be addressed.
Still referring to Table 1, for a current density of 0.93xc3x97106 amps/cm2, 616 violations must be corrected before the current density design limit is satisfied. Thus, increasing the allowable current density design limit from 0.93xc3x97106 to 3.17xc3x97106 amps/cm2 decreases the number of violations which must be satisfied from 616 violations to nine violations. Thus, the case illustrated by Table 1 shows that for an increase in the current density limit of approximately four times the number of violations that must be corrected is reduced by over 98%, a non-linear relationship. A preliminary VLSI design can have 2.1 million violations or more. Thus, increasing the allowable current density limit can have a significant impact on the number of potential violations to be addressed in a redesign.
FIG. 1B is a graph of the number of interconnects versus the current density distribution. As shown in FIG. 1B (and as previously noted in Table 1), the relationship between the number of interconnects and the current density distribution is non-linear. Thus, an increase in the allowable current density can be expected to disproportionately lower the number of violations.
The relation between the divergence of atomic flux and the time to failure can also be modeled mathematically. FIG. 3 shows the probability distribution function of the time to failure as a lognormal distribution. Thus, FIG. 3 shows the probability of failure at a given time. The area under the curve is normalized to one so that the percentage of failed devices can be calculated by integrating the area under the curve from time to failure equal zero (TTF=0) to the time of interest.
The percentage of failed devices at a given time based on the probability distribution function of the time to failure can also be estimated. FIG. 4 shows the cumulative distribution function in conjunction with the probability distribution function. The cumulative distribution function (CDF) defines the percentage of failed devices as a function of time. Based on the CDF the reliability can be calculated at a given time.
Data from accelerated testing are often used to estimate the failure distribution of each class of interconnect structures. Testing is accelerated using higher currents and temperatures than normal operating conditions. Often, the mode of failure in the accelerated test is assumed to be the same (or similar) to the failure mode under normal operating conditions. The failure distribution can be extrapolated for normal operations. Computer aided design tools determine the relative current stress Sy and temperature acceleration factor Ay at worst case operating conditions.
Designers can permit a certain number of connections which do not satisfy the reliability goal. Designing a circuit including a connection with greater than the current density design limit is known as xe2x80x9cwaiving an errorxe2x80x9d or xe2x80x9cwaiving a violation.xe2x80x9d What is needed is a method to determine the number of violations which can be waived considering the temperature effects.
The interconnect system of layouts of VLSI designs are analyzed with respect to the electromigrations risk in order to ensure a reliable design. The electromigration risk is directly proportional to the current density and temperature. The current density can be obtained from electrical simulations for the metal lead and via system. The temperature can be estimated by thermal simulation. Thermal simulation can be performed using power dissipation of the circuitry as input. Based on simulations, calculated current densities can be compared to a current density limit. If the current density exceeds the current density limit the interconnect is identified for redesign. The number of such interconnects identified is usually very high. Thus, it can be necessary to waive a certain number of such violations.
The method taught uses the obtained current density and temperature distribution to predict which interconnects have to be redesigned in order to meet the reliability criteria. Thus, the method taught can determine the number of interconnects which must be redesigned to satisfy the reliability criteria. Thus, based on the reliability goal for the entire design specific, reliability levels will be assigned to blocks or parts of the design. After the layout phase the design of these blocks can be analyzed according to the method taught. The method allows analysis of part of a design and does not require analysis of an entire design.
In order to determine the number of violations which need to be addressed, the tool can perform an analysis assuming the violations above a certain level have been addressed. Based on the number of violations which have been addressed the method can calculate a new reliability. If the reliability is below the reliability criteria, the level of which violations have to be fixed will be lowered and the process starts again until the given reliability criteria is met. Therefore, the output is a specific list identifying the interconnect portions which are to be redesigned to meet the reliability criteria. The method can also identify an approximate amount by which to widen a metal lead to meet the desired reliability criteria.
The foregoing is a summary and this contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting.